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NCP3125
In a typical converter design, the ESR of the output
capacitor bank dominates the transient response. Please note
that D V OUT ? DIS and D V OUT ? ESR are out of phase with each
other, and the larger of these two voltages will determine the
maximum deviation of the output voltage (neglecting the
effect of the ESL).
Input Capacitor Selection
The input capacitor has to sustain the ripple current
produced during the on time of the upper MOSFET, so it
Starting with the high ? side MOSFET, the power
dissipation can be approximated from:
P D_HS + P COND ) P SW_TOT (eq. 21)
P COND = Conduction power losses
P SW_TOT = Total switching losses
P D_HS = Power losses in the high side MOSFET
The first term in Equation 21 is the conduction loss of the
high ? side MOSFET while it is on.
must have a low ESR to minimize the losses. The RMS value
of the input ripple current is:
P COND + I RMS_HS
2
@ R DS(on)_HS
(eq. 22)
Iin RMS + I OUT D (1 * D) 3
1.79 A + 4 A * 27.5 * (1 * 27.5)
(eq. 19)
I RMS_HS
R DS(on)_HS
P cond
= RMS current in the high ? side MOSFET
= On resistance of the high ? side MOSFET
= Conduction power losses
I RMS_HS + I OUT @
D @ 1 )
D = Duty ratio
IIN RMS = Input capacitance RMS current
I OUT = Load current
The equation reaches its maximum value with D = 0.5.
Using the ra term from Equation 5, I RMS becomes:
ra 2
12
(eq. 23)
P CIN + CIN ESR * IiN RMS 3
32 mW + 10 m W * 1.79 A
Loss in the input capacitors can be calculated with the
following equation:
2
(eq. 20)
2
CIN ESR = Input capacitance Equivalent Series
Resistance
IIN RMS = Input capacitance RMS current
P CIN = Power loss in the input capacitor
Due to large di/dt through the input capacitors, electrolytic
or ceramics should be used. If a tantalum must be used, it
must be surge protected, otherwise, capacitor failure could
occur.
Power MOSFET Dissipation
MOSFET power dissipation, package size, and the
I RMS_HS = High side MOSFET RMS current
I OUT = Output current
D = Duty ratio
ra = Ripple current ratio
The second term from Equation 21 is the total switching
loss and can be approximated from the following equations.
P SW_TOT + P SW ) P DS ) P RR (eq. 24)
P DS = High side MOSFET drain source losses
P RR = High side MOSFET reverse recovery losses
P SW = High side MOSFET switching losses
P SW_TOT = High side MOSFET total switching losses
The first term for total switching losses from Equation 24
are the losses associated with turning the high ? side
MOSFET on and off and the corresponding overlap in drain
voltage and current.
thermal environment drive power supply design. Once the
dissipation is known, the thermal impedance can be
calculated to prevent the specified maximum junction
P SW + P TON ) P TOFF
2
+ 1 @ I OUT @ V IN @ F SW @ t RISE ) t FALL
(eq. 25)
temperatures from being exceeded at the highest ambient
temperature.
Power dissipation has two primary contributors:
conduction losses and switching losses. The high ? side
MOSFET will display both switching and conduction
losses. The switching losses of the low side MOSFET will
not be calculated as it switches into nearly zero voltage and
the losses are insignificant. However, the body diode in the
low ? side MOSFET will suffer diode losses during the
F SW
I OUT
t FALL
t RISE
V IN
P SW
P TON
P TOFF
= Switching frequency
= Load current
= MOSFET fall time
= MOSFET rise time
= Input voltage
= High side MOSFET switching losses
= Turn on power losses
= Turn off power losses
non ? overlap time of the gate drivers.
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